1. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor:

Label1:	LW $1, 40($6) BEQ $2, $3, Label2 ; Taken ADD $1, $6, $4
Label2:	BEQ $1, $2, Label1 ; Not Taken SW $2, 20($4)

AND $1, $1, $4

1. Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.

2. Repeat 1.1, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch.

3. For the given code, what is the speedup achieved by moving branch execution into the ID stage? Explain your answer. In your speedup calculation, assume that the additional comparison in the ID stage does not affect clock cycle time.