Question: Assume that the instruction is executed in a single - cycle datapath. The Following instruction was fetched: 0 0 0 0 0 0 1 0

Assume that the instruction is executed in a single-cycle datapath. The Following instruction was fetched:
00000010000100001000000000100000
Assume the data memory is all zeros and that the processor's registers have the following values at the beginning of the clock cycle in which the above instruction word is fetched:
\table[[r0,r1,r2,r3,r4,r5,r16,r8,r12,r31],[0,1,4,2,-2,15,8,6,2,-4]]
What are the outputs of the sign-extend the shift-2 unit for this instruction word?
What are the values of the ALU control unit's inputs for this instruction?
For each Mux, show the values of its data output during the execution of this instruction and these register values
For the ALU and the two add units, what are their data input values?
What are the values of all inputs for the "registers" unit?
Assume that the instruction is executed in a single-cycle datapath. The Following instruction was fetched:
00000010000100001000000000100000
Assume the data memory is all zeros and that the processor's registers have the following values at the beginning of the clock cycle in which the above instruction word is fetched:
\table[[r0,r1,r2,r3,r4,r5,r16,r8,r12,r31],[0,1,4,2,-2,15,8,6,2,-4]]
What are the outputs of the sign-extend the shift-2 unit for this instruction word?
What are the values of the ALU control unit's inputs for this instruction?
For each Mux, show the values of its data output during the execution of this instruction and these register values
For the ALU and the two add units, what are their data input values?
What are the values of all inputs for the "registers" unit?
Assume that the instruction is executed in a

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