Assume the scoreboarded architecture has $2$ load$/$store functional units, $1$ integer ALU unit $($which does not handle either divide or multiply$),2$ functional units for multiplication, $1$ functional unit for floating point addition, and $1$ functional

unit for division. Assume the scoreboard has a buffering capacity of one instruction in RO and one in WB$.$

What does the functional units mean here, so for example if the architecture has

$2$ load$/$store functional units meaning that MEM stage has two units where we can perform two load$/$ two store $($I$.$e $2$ writes$/$reads$)$or one load & one store $(1$ read & $1$ write$)$ from memory in the same clock cycle in RISC $-$ V $??$

And what is the difference between number of cycles in EX and number of functional units. Explain with examples??