Assume you have a processor with a 16KB, 4-way set-associative (i.e., each set consists of 4 blocks) data cache with 32-byte blocks.

a) How many total blocks are in the cache? How many sets are there?

b) Assuming that memory is byte addressable and addresses are 35-bits long, give the number of bits required for each of the following fields: cache tag, index, and byte offset.

Cache Tag
Index
Byte Select

c) Draw a block diagram for this cache organization. Show a 35-bit address coming into the diagram and a 32-bit data result and Hit signal coming out. Include all of the comparators in the system and any muxes as well. Include the data storage memories (indexed by the Index), the tag matching logic, and any muxes. Make sure to label address widths and data widths. Make sure to label the function of various blocks and the width of any buses.

d) Draw a diagram that shows the mapping between cache and main memory.