Question: B . ( 5 points ) The MSP 4 3 0 F 5 5 2 9 receives interrupt requests from the watchdog timer in the

B.(5 points) The MSP430F5529 receives interrupt requests from the watchdog timer in the interval mode (WDT) and parallel ports P1.7 and P2.2 during execution of an instruction that takes 6 clock cycles to execute. P1 is received in the 1st clock cycle of the instruction execution, WDT is received in the 5th clock cycle, and P2 in the 3rd clock cycle. Which ISR is accepted and processed first, assuming all interrupts are enabled and GIE=1? Hint: Inspect IVT for determining priorities.

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