Question: b ) Draw the circuit diagram of a basic logic element ( BLE ) used in an FPGA and show how its functionality can be

b) Draw the circuit diagram of a basic logic element (BLE) used in an FPGA and show how its functionality can be programmed and reprogrammed in the field. Describe the three different methods which can be used for storing the programming bits and compare and contrast them citing advantages and disadvantages of each.
c) Draw the diagram of an FPLS with 2 storage elements, 3 primary inputs and three primary outputs and explain how multiplexers can be used to implementing the programming of the OR plane, the AND plane and the final output stage of exclusive OR gates.
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a)
4a) Figure Q.4 is that of a 6 bit by 6 bit parallel hardware multiplier. Use it to multiply the two unsigned decimal numbers 49 and 53 and verify the product. Write down the state of each internal node.
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b) To speed up the parallel hardware multiplication and reduce the effects of ripple carry along each row, carry look ahead can be used at each stage. At the \( i^{\text {th }}\) stage a carry can be generated: \(\boldsymbol{G}_{\boldsymbol{i}}\) or propagated from the previous stage (i-1)\(\boldsymbol{P}_{\boldsymbol{i}}\). Assuming the two inputs to be added at each stage are \(\boldsymbol{A}_{\boldsymbol{i}}\) and \(\boldsymbol{B}_{\boldsymbol{i}}\), write down general equations for \(\boldsymbol{G}_{\boldsymbol{i}}\) and \(\boldsymbol{P}_{\boldsymbol{i}}\) for the \(\boldsymbol{i}^{\text {th }}\) stage.
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c) Develop equations for \(\boldsymbol{P}_{\mathbf{0}}\) and \(\boldsymbol{G}_{\mathbf{0}}\) through \(\boldsymbol{P}_{\mathbf{3}}\) and \(\boldsymbol{G}_{\mathbf{3}}\). Hence explain the drawback of this approach for large multipliers.
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b ) Draw the circuit diagram of a basic logic

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