Question: Below are two Verilog codes. One for a 4-bit counter, and one for a hex to 7-segment decoder. Create a module to connect the two.

Below are two Verilog codes. One for a 4-bit counter, and one for a hex to 7-segment decoder. Create a module to connect the two. So the output of the counter will be an input to the decoder. Also create a verilog testbench to display the clock input, 4 counter outputs, and the 7 outputs of the decoder.

//Hex to 7-seg module lab_x_behavioral (SW, HEX0);

input [3:0] SW; output [6:0] HEX0; bcd_behavioral u0 (SW[3:0], HEX0[6:0]); endmodule

module bcd_behavioral (bcd, HEX0); input [3:0] bcd; output reg [6:0] HEX0; always @(bcd) begin case (bcd) 4'b0000: HEX0 <= ~7'b0111111; 4'b0001: HEX0 <= ~7'b0000110; 4'b0010: HEX0 <= ~7'b1011011; 4'b0011: HEX0 <= ~7'b1001111; 4'b0100: HEX0 <= ~7'b1100110; 4'b0101: HEX0 <= ~7'b1101101; 4'b0110: HEX0 <= ~7'b1111101; 4'b0111: HEX0 <= ~7'b0000111; 4'b1000: HEX0 <= ~7'b1111111; 4'b1001: HEX0 <= ~7'b1101111; 4'b1010: HEX0 <= ~7'b1110111; 4'b1011: HEX0 <= ~7'b1111100; 4'b1100: HEX0 <= ~7'b0111001; 4'b1101: HEX0 <= ~7'b1011110; 4'b1110: HEX0 <= ~7'b1111001; 4'b1111: HEX0 <= ~7'b1110001; endcase end endmodule

----------------------------------------------------------------

//4-bit counter counting from 0000 to 1111

module lab_x_counter (clk, cnt);

input clk; output reg[3:0] cnt;

always @(posedge clk) begin cnt <= cnt + 1; end

initial cnt <= 0; endmodule

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