Below is the code in VHDL for a sn74163 counter modify the code in order for it to act as a sn74162 counter. Must be written in VHDL!!! ALl the inputs should stay the same only thing you should have to change is if statements and the COUT. PLz show all code!

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity sn74163 is

port(

ClrN: in std_logic;

LdN: in std_logic;

P: in std_logic;

T: in std_logic;

clk: in std_logic;

D: in std_logic_vector(3 downto 0);

Cout:out std_logic; Q: out std_logic_vector(3 downto 0)

);

end sn74163;

architecture behavior of sn74163 is

signal Qint: unsigned(Q'range);

begin

process(clk)

begin

-- note the use of the 'last_value attribute

-- to confirm the previous value of the clock

if( clk'event and clk'last_value='0' and clk='1') then

if(clrN='0') then Qint<="0000";

elsif(LdN='0') then Qint<=unsigned(D);

elsif(P='1' and T='1') then Qint<=Qint+1;

end if;

end if;

end process;

Q<=std_logic_vector(Qint);

Cout<=Qint(3) and Qint(2) and Qint(1) and Qint(0) and T;

end behavior;