Build a 4 bit ALU, stringing together four 1 bit ALU's (the last one with overflow detection and SET output), that does addition, subtraction, and, or, and set on less than. Use good hierarchal design and keep the Verilog code as elementary as possible. Create a separate module for the instance of the 4-bit ALU.

Base your answer off of the following ALU definition:

module ALU (ALUctl, A, B, ALUOut, Zero);

input [2:0] ALUctl; input [3:0] A,B; output reg [3:0] ALUOut; output Zero; assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0;

always @(ALUctl, A, B) //reevaluate if these change

case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1:0; default: ALUOut <= 0; endcase

endmodule