build a circuit diagram $($ie Logisim$/$Circuitverse$)$ for an active high, rising edge d flip flop using only AND, NOT, and OR gates, with an edge detector. Include a detailed timing diagram of the edge detector circuit that demonstrates the timing delay and the resultant edge pulse created by the NOT gate$($s$)$ is enough to trigger the AND gate. You will need to consider the minimum pulse width the AND gate requires, and the propagation delays created by the NOT gates.