Build the gates described in Chapter $2($see table below$),$ which will test your

understanding of Boolean Logic and Arithmetic, building the gates that do so$.$

Grading method:

If the chip passes all the tests specified in the supplied test script, it receives $60\%$ of the

grade. $30\%$ goes to it being well built $($the lowest number of chips to implement$),$ with the

remaining $10\%$ going towards documentation provided for each chip. Generally speaking, we

prefer implementations that use as few chip parts as possible, even if it implies a less efficient

chip design $($in terms of # of AND$/$OR$/$NOT chips$).$ Higher$-$level chips are considered as one chip

part $($ex$.$ Mux, DMux, Or$8$Way, etc.$)$

What do you turn in$?$

What do you turn in$?$

A Word document $($or PDF$)$ with screen shots of each of the working $($or not$)$ logic gates.

You should also upload the documentation.pdf file $($see Documentation Instructions for

guidelines on how to do this$)$ per Project Submission Guidelines.

NOTE: the HDL code you write for the ALU $($ALU$.$hdl$)$ will be used in BOTH test

scripts $($ALU$-$nostat.tst and ALU.tst$).$ Please take a screen shot of the output from both tests.

This is to maximize partial credit for you in case you aren$$t able to get the status output flags

working.

Chip Working? Well built?

HalfAdder $/10/5$

FullAdder $/10/5$

Add$16/10/5$

Inc$16/10/5$

ALU $+$ no status

outputs $($ALU$-$

nostat.tst$)$

$/15/5$

ALU $+$ full test

$($ALU$.$tst$)/5/5$

Subtotal $/60/30$

Documentation $/10$