c) Consider a CPU supporting superscalar processing. This CPU has one fetch unit, two decode units, two execute units and two write units. The fetch unit can fetch four instructions in one clock cycle. All instructions require 4 steps: fetch, decode, execute and write-back. Each step takes one clock cycle. Calculate the performance gained (compared to the case in which instruction pipeline is not available) in terms of number of clock cycle. Draw a diagram to explain your answer. [9]