Caches are important to providing a high$-$performance memory hierarchy to processors. Below is a list of $32-$bit memory address references, given as word addresses.

$3,180,43,2,191,88,190,14,181,44,186,253$

a$.$ For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with $16$ one$-$word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.

NOTE : the question is the samw with this diffrence: $8$ blocks means $3-$bits index, block, offset$=1($the solution should be with a table as the solution in main question$).$

Part C: BASED ON THE SAME QUESTION,

You are asked to optimize a cache design for the given references. There are three direct$-$mapped cache designs possible, all with a total of $8$ words of data: C$1$ has $1-$word blocks, C$2$ has $2-$word blocks, and C$3$ has $4-$word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is $25$ cycles, where C$1$ has an access time of $2$ cycles, C$2$ takes $3$ cycles, and C$3$ takes $5$ cycles, which is the best cache design? $($Image Include the reminder of question$)$