Calculate the maximum clock frequency for the single cycle RISC-V processor you studied given - Any MUX delay: 80ps - Any gate delay: 40ps - Decoding (control unit and ALU Control unit) delay: 80ps (2-level logic) - Adder delay: 520ps - ALU delay: 600ps - Memory read delay: 2 ns (i.e., 2000 ps) - Data must be present @ the memory input 20 ps before the clock edge - Register File (RF) read delay: 50 ps - Data must be present @ the RF input 10 ps before the clock edge - Immediate Generator delay: 15 ps - Shift left 1 delay: 5ps - PCtsu and tCQ=25ps