Any MUX delay: 80 ps Any gate delay: 40 ps Decoding (control unit and ALU Control unit) delay: 80 ps (2-level logic) Adder delay: 520 ps ALU delay: 600 ps Memory read delay: 2 ns (i.e., 2000 ps) Data must be present @ the memory input 20 ps before the clock edge Register File (RF) read delay: 50 ps Data must be present @ the RF input 10 ps before the clock edge Immediate Generator delay: 15 ps Shift left 1 delay: 5 ps PC tsu and tCQ = 25 ps Problem 3: Draw a simplified datapath for the single cycle RISC-V processor that supports the BEQ, LW, and SW instructions only. Using the delays given, what would be the maximum clock frequency in this case?