Can someone please show me the steps to solving the problem below?

Given the read cycle diagram below, how long does memory have to put the data on the bus after the MREQ# line is asserted assuming a bus clock of 82.7-MHz and 7 wait states? (Give your answer in ns to one decimal place.) Read Cycle with One Wait State ADDRESS Memory Address to be Read DATA Data Read MREQ# WAIT # TAD-9.4 ns max TML1.5 ns min TM = 6 ns max TRL-2.2 ns max TDs 6.4 ns min TMH = 1.7 ns max TRH 2.6 ns max TDH = 0.3 ns min Given the read cycle diagram below, how long does memory have to put the data on the bus after the MREQ# line is asserted assuming a bus clock of 82.7-MHz and 7 wait states? (Give your answer in ns to one decimal place.) Read Cycle with One Wait State ADDRESS Memory Address to be Read DATA Data Read MREQ# WAIT # TAD-9.4 ns max TML1.5 ns min TM = 6 ns max TRL-2.2 ns max TDs 6.4 ns min TMH = 1.7 ns max TRH 2.6 ns max TDH = 0.3 ns min