Given the read cycle diagram below, how long does memory have to put the data on the bus after the MREQ# line is asserted assuming a bus clock of $23\mathrm{.}7-MHz$ and $7$ wait states? $($Give your answer in $ns$ to one decimal place.$)$

$T_{AD}=9\mathrm{.}9ns$ max

$T_{ML}=2ns$ min

$T_M=5\mathrm{.}3ns$ max

$T_{RL}=2\mathrm{.}9ns$ max

$T_{DS}=5\mathrm{.}3ns$ min

$T_{MH}=1\mathrm{.}3ns$ max

$T_{RH}=2\mathrm{.}8ns$ max

$T_{DH}=0\mathrm{.}8ns$ min