Can you draw the hardware out for me$.$

Problem $1$: Show the hardware that will be synthesized for the posted solution to Homework $5.$

The solution $($with fewer comments than the posted version$)$ is shown below.

$```$

module dot$\_$seq$\_2$ #$($ int w $=5,$ wi $=4)$

$($ output logic $[$w$-1$:$0]$ dp$,$ output logic $[$wi$-1$:$0]$ first$\_$id$,$ last$\_$id$,$

input uwire $[$w$-1$:$0]$ a$[2],$ b$[2],$ input uwire $[$wi$-1$:$0]$ in$\_$id$,$

input uwire reset, first, last, input uwire clk $)$;

logic $[$w$-1$:$0]$ pl$\_$a$[1$:$1][2],$ pl$\_$b$[1$:$1][2]$; $//$ Arriving vector elements.

logic $[$w$-1$:$0]$ pl$\_$prod$[2$:$2][2]$; $//$ Vector products.

logic $[$w$-1$:$0]$ pl$\_$sum$[3$:$3]$; $//$ Dot prod of $2-$element segment.

logic $[$wi$-1$:$0]$ pl$\_$id$[1$:$3]$; $//$ ID$.$

logic $[1$:$0]$ pl$\_$fl$[1$:$3]$; $//$ The first and last signals.

logic $[$wi$-1$:$0]$ acc$\_$id;

logic $[$w$-1$:$0]$ acc$\_$sum;

always$\_$ff @$($ posedge clk $)$ begin

$///$ Stage $0$

pl$\_$a a; $//$ This copies both elements of a$.$

pl$\_$b b;

pl$\_$id in$\_$id;

pl$\_$fl reset $?2\text{'}$b$0$ : $\{$last$,$first$\}$;

$///$ Stage $1$

for $($ int i$=0$; i$<mn>2</mn>$; i$++)$ pl$\_$prod$[2][$i pl$\_$a$[1][$i$]*$ pl$\_$b$[1][$i$]$;

pl$\_$id pl$\_$id$[1]$;

pl$\_$fl reset $?2\text{'}$d$0$ : pl$\_$fl$[1]$;

$///$ Stage $2$

pl$\_$sum pl$\_$prod$[2][0]+$ pl$\_$prod$[2][1]$;

pl$\_$id pl$\_$id$[2]$;

pl$\_$fl reset $?2\text{'}$h$0$ : pl$\_$fl$[2]$;

$///$ Stage $3$

begin

automatic logic s$3\_$first $=$ pl$\_$fl$[3][0]$; $//$ For readability.

automatic logic s$3\_$last $=$ pl$\_$fl$[3][1]$; $//$ For readability.

automatic logic $[$w$-1$:$0]$ s$3\_$sum $=$ s$3\_$first $?$ pl$\_$sum$[3]$ : pl$\_$sum$[3]+$ acc$\_$sum;

acc$\_$sum s$3\_$sum;

if $($ reset $)$ begin

first$\_$id ;

last$\_$id ;

end else begin

if $($ s$3\_$first $)$ acc$\_$id pl$\_$id$[3]$;

if $($ s$3\_$last $)$ begin

first$\_$id s$3\_$first $?$ pl$\_$id$[3]$ : acc$\_$id;

last$\_$id pl$\_$id$[3]$;

dp s$3\_$sum;

end

end

end

end

endmodule

$```$