CEDAR LOGIC design

Can you please design circuits representing the following cases using Logical gates via CEDAR LOGIC program?

M1(A,V,L,S) = A'V'L'S+A'V'L'S+AV'L'S'+AV'L'S = V'L' M2(A,V,L,S) = A'VL'S'+A'VL'S+A'VLS'+A'VLS+AVL'S'+AVL'S+AVLS'+AVLS = V M3(A,V,L,S) = A'V'LS'+A'V'LS+A'VLS'+A'VLS+AV'LS'+AV'LS+AVLS'+AVLS = L M4(A,V,L,S) = A'V'L'S+A'V'LS+AV'L'S+AV'LS = VS M5(A,V,L,S) = AVLS+AVLS = VLS