circuit must detect a 01 sequence. The sequence sets z= 1,which is reset only by a 00
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circuit must detect a 01 sequence. The sequence sets z= 1,which is reset only by a 00 sequence. For all other cases, z = 0. Overlap is allowed in the sense that the second bit of the reset sequence “00” can be counted as the first bit of the next set sequence “01.” For example, for input sequence x as follows, the corresponding output sequence z would be:
x = 010100100
z = 01111011
Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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