cmd Create a truth table for this circuit: 3. AIB A B 0 The symbol means a "constant 0". and symbol ? means a "constant !" Complete the timing diagram of the circuit whose VHDL deseription is shown below use ieee.atd logio 116s.all, process (ztn, alk, a, b, x) begin if rstn ? 10, then elif (clk' event and clk ,1") then it1' then t a and b end if: end ifi end process end bhr: truth table for the following shift register (initial state Q,-Q,-Q?Qi=0,--o e a synchronous reset). Oo Reset D Q CLK Reset | CLK | D | Q4 mode initial storage