CMPEN $270$: Digital Design: Theory and Practice Module $7$ Homework

Name: $q,$ This work is entirely my own and I did not provide any assistance to anyone else except as noted.

$($signature$)q,$

Problems

Show your work for each problem.

$(3$ points$)$ Design a $D$ flip$-$flop with a synchronous, active high set input. Inputs to the flip$-$flop are D$,$ CLK and SET, the output is $Q.$ Make a truth table and draw the circuit below.

$(3$ points$)$ A timing diagram is given for inputs to an SR latch. Answer the questions and complete the timing diagram for the $Q$ output of the SR latch. Assume the delay from inputs changing to the output changing is negligible.