Question: code this in verilog with adder seven segment Problem Specification: DLD Lab has a total of 30 marks and split into the following components: Design

code this in verilog with adder seven segment

Problem Specification: DLD Lab has a total of 30 marks and split into the following components: Design a logic circuit that take the marks for each of the above components as input. It determines and displays the total marks in the lab. Also, it displays the lab grade based on the following grading scheme. This is a sample display. You can design a different display to provide the requested functionality

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