Question: - Complete the given Verilog code for translating the 4 bit number into 7 segment coding. module hex7seg (x,En,a_to_g); input [3:0]x; output En; output reg

- Complete the given Verilog code for translating the 4 bit

- Complete the given Verilog code for translating the 4 bit number into 7 segment coding. module hex7seg (x,En,a_to_g); input [3:0]x; output En; output reg [6:0] a_ to g; always@(*) begin case (x) 0: a_ to g= 1: a_to g= 2: a_to g= 3: a_to g= 4: a_to g= 5: a_to g= 6: a_to g= 7: a_to g= 8: a_to g= 9: a_to g= hA: a to g= hib: a_ to g = 'hC: a to g= 'hd: a_to g= 'hE: a to g= 'hF: a to g= default: a to g=7 7'b1111110; endcase end assign En=0; endmodule

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