Complete the Table $2.$ based on the given information. $[2$ pts$]$

Consider a hypothetical architecture where the opcodes for certain operations and available

registers are made available to you. This architecture uses a two$-$address instruction format

with register$-$direct or immediate addressing modes. The syntax for each instruction is $-$

OPCODE dest, source$1,$ source $2$

The destination for the output of each operation is always a register while the operands can be

from registers or immediately mentioned in the instruction itself. For example if the assembly

instruction is ADD R$1,$ R$2,$ then the actual operation can be viewed as R$1RR1+R2.$

Complete the binary encoding for the given instructions. If the source operand is not a register,

compute the binary encoding in $6-$bit format and write it under the IMMD column. $[3$ pts$]$

Table $1.$ Table with binary encoding for opcode and registers.

Complete Table $2.$ by filling in the corresponding binary encoding for each instruction given in

assembly language.