Question: Complete the timing diagram below for a falling edge triggered J K flip-flop with asynchronous active-low CLR (CLR-N) and SET (PRE-N) inputs. Output Q starts

Complete the timing diagram below for a falling edge triggered J K flip-flop with asynchronous active-low CLR (CLR-N) and SET (PRE-N) inputs. Output Q starts in the 0 state. Show all significant cause/effect arrows

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