Complete the VERILOG sequence generator

R0=4; Repeat R0=5*R0

Complete the sequence generator that produces the sequence: 4, 20, 100, 500, ... . The initial value is 4, each following value is multipled by 5.

The controller can be done using 9 states. First draw a state graph of the controller, then complete the provided FSM. The reset and first state are already completed.

module controller( output as_ctl_t as_ctl, output shift_ctl_t shift_ctl, output logic r1_ld, r0_ld, output logic ready, input logic next, input clk, reset ); logic [3:0] step; task ctrl(logic rdy, as_ctl_t as, shift_ctl_t sh, logic r1, logic r0 ); begin ready <= rdy; as_ctl <= as; shift_ctl <= sh; r1_ld <= r1; r0_ld <= r0; end endtask always_ff @(posedge clk) begin if ( reset ) begin step <= 0; ctrl(0, AS_A, SH_PASS, 0, 0 ); end else begin case( step ) 0: begin // R0 = 1 step <= step + 1; ctrl(0, AS_A, SH_ONE, 0, 1 ); end // complete the rest endcase end end endmodule