VERILOG sequence generator, complete the code:

R0=1; Repeat R0=15*R0

Complete the sequence generator that produces the sequence: 1, 15, 15*15, 15*15*15, ... . The initial value is 1, each following value is multipled by 15.

The controller can be done using 5 states. First draw a state graph of the controller, then complete the provided FSM. The initial state is already completed.

module controller( output as_ctl_t as_ctl, output shift_ctl_t shift_ctl, output logic r1_ld, r0_ld, output logic ready, input logic next, input clk, reset ); logic [2:0] step; task automatic ctrl( logic rdy, as_ctl_t as, shift_ctl_t sh, logic r1, logic r0 ); ready <= rdy; as_ctl <= as; shift_ctl <= sh; r1_ld <= r1; r0_ld <= r0; endtask always_ff @(posedge clk) begin if ( reset ) begin step <= 0; // R0 = 1 ctrl(0, AS_A, SH_ONE, 0, 1 ); end else begin case( step ) 0: begin // hint: this is the ready state end 1: begin // end 2: begin // end 3: begin // state <= 0; end endcase end end endmodule