Complete the VERILOG sequence generator RO 4; Repeat RO-5 RO Complete the sequence generator that produces the sequence: 4, 20, 100, 500, . The initial value is 4 each following value is multipled by 5. The controller can be done using 9 states. First draw a state graph of the controller, then complete the provided FSM. The reset and first state are already completed. module controller( output as_ctl_t as_ctl, output shift_ctl_t shift_ctl, output logic r1_ld, rO_ld, output logic ready input logic next, input clk, reset logic [3:0] step; task ctrl(logic rdy, as_ctl_t as, shift_ctl_t sh, logic r1, logic rO) in ready