Computer Arch

Part A Assume the following For this cache, list all of the hexadecimal memory addresses that wll hit in set 3. Check all that apply. The memory is byte addressable Memory accesses are to 1-byte words (not to 4-byte words). . Addresses are 13 bits wide 0x0620 Ox062D 0x062E 0x062F 0x064C 0x064D 0x064E 0x064F O 0x051C 0x051D 0x051E 0x051F The cache is two-way set associative (E 2), with a 4-byte block size (B 4) and eight sets (S 8) The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Line 0 Line 1 Set Byte Byte Byte Byte 0 1 3 Tag Valid Byte Byte Byte Byte 0 123 index Tag Valid Valid 0 09 186 30 3F 10 00 0- 45 1 60 4F EO 23 38 1 00 BC OB 37 EB 0 06 0 C7 1 06 78 07 C5 051 40 67 C23B 71 1 0B 0- 32 1 12 08 7B AD Submit Request Answer 7 46 0 DE 1 12CO 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following CO. The cache block offset Cl. The cache set index CT. The cache tag Provide Feedback