Computer Architecture

Please explian. don't just post the solution, i already have that.

Part A Assume the following For this cache, list all of the hexadecimal memory addresses that will hit in set 3. The memory is byte addressable Memory accesses are to 1-byte words (not to 4-byte words) Addresses are 13 bits wide The cache is two-way set associative (E 2), with a 4-byte block Check all that apply 0x062C 0x062D 0x062E 0x062F 0x064C 0x064D 0x064E 0x064F 0x051C 0x051D 0x051E 0x051F size (B 4) and eight sets (S 8) The contents of the cache are as follows, with all numbers given in hexadecimal notation. 2-way set associative cache Line 0 Line 1 Set index Tag Valid l Byte Byte Byte Byte Tag valid 'ytol,-2 Byte Byte Byte 0 09186 30 3F 10 00 0 -- 45 1 60 4F E0 2338 100BC OB 37 EB 0 06 0 C7 1 06 78 07 C505 14067 C2 3B --OB 0 -32 1 12 08 7B AD 2 4 5 71 1OB DE 18 4B 6E 0 91 1 A0 B7 26 2DFO 0 7 46 -DE 1 12 CO 88 37 Submit uest Answer The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following CO. The cache block offset Cl. The cache set index CT. The cache tag Provide Feedback