Computer Architecture question:

Your branch target buffer (and branch history buffer) each have 8 slots. Your CPU executes the follow- ing code fragment. Assume that prediction takes place in the Fetch cycle, and that the result of a branch is actually known after the eXecute cycle. Assume full forwarding (MX, WX. WM). Also, assume that array100, 150, 200, 250, 300) addi x12, x0, 5 add x11, x0, x0 add x19, x0, x0 addi x20, x0, 150 // x12=5 // x110 // x19 // x20 150 bge x11, x12, Exit slli x13, x11, 3 add x14, x16, x13 ld x15, 0Cx14) blt x15, x20, L2 sd x0, 0(x14) add x19, x15, x19 beq x, x0, L3 //x16 address of array [0] L2: addi x15, x15, 1 sd x15, 0(x14) L3: addi x11, x11, 1 jal x0, L1 Exit: (a) Draw a partial pipeline diagram for the execution of the program. This partial pipeline diagram needs to show every (consecutive) pair of instructions between which a stall is necessary, but it need not show instruction pairs if there's no s Assume a static predict-not-taken policy (yes, this means that the BTB and BHT aren't used et). Circle the stages in which the outcome of a branch is known. Make sure to include stalls due to branch misprediction. How many cycles are lost due to stalls? (b) Assume that you are using a 1-bit branch predictor, and redraw the partial pipeline diagram. How many ate the cycle in which the outcome of a branch (c) Show the values read and written from the BTB and BHT (from3b and the cycles in which the read/write (d) Assume that you are using a 2-bit branch predictor, and redraw the partial pipeline diagram. How many cycles are lost due to stalls? Make sure that you incorpor is known, if necessary occurs. You need not show reads due to fetches of non-branch instructions. cycles are lost due to stalls? Make sure that you incorpor is known, if necessary ate the cycle in which the outcome of a branch (e) Show the values read and written from the BTB and BHT (fromBd and the cycles in which the read/write occurs. You need not show reads due to fetches of non-branch instructions. Your branch target buffer (and branch history buffer) each have 8 slots. Your CPU executes the follow- ing code fragment. Assume that prediction takes place in the Fetch cycle, and that the result of a branch is actually known after the eXecute cycle. Assume full forwarding (MX, WX. WM). Also, assume that array100, 150, 200, 250, 300) addi x12, x0, 5 add x11, x0, x0 add x19, x0, x0 addi x20, x0, 150 // x12=5 // x110 // x19 // x20 150 bge x11, x12, Exit slli x13, x11, 3 add x14, x16, x13 ld x15, 0Cx14) blt x15, x20, L2 sd x0, 0(x14) add x19, x15, x19 beq x, x0, L3 //x16 address of array [0] L2: addi x15, x15, 1 sd x15, 0(x14) L3: addi x11, x11, 1 jal x0, L1 Exit: (a) Draw a partial pipeline diagram for the execution of the program. This partial pipeline diagram needs to show every (consecutive) pair of instructions between which a stall is necessary, but it need not show instruction pairs if there's no s Assume a static predict-not-taken policy (yes, this means that the BTB and BHT aren't used et). Circle the stages in which the outcome of a branch is known. Make sure to include stalls due to branch misprediction. How many cycles are lost due to stalls? (b) Assume that you are using a 1-bit branch predictor, and redraw the partial pipeline diagram. How many ate the cycle in which the outcome of a branch (c) Show the values read and written from the BTB and BHT (from3b and the cycles in which the read/write (d) Assume that you are using a 2-bit branch predictor, and redraw the partial pipeline diagram. How many cycles are lost due to stalls? Make sure that you incorpor is known, if necessary occurs. You need not show reads due to fetches of non-branch instructions. cycles are lost due to stalls? Make sure that you incorpor is known, if necessary ate the cycle in which the outcome of a branch (e) Show the values read and written from the BTB and BHT (fromBd and the cycles in which the read/write occurs. You need not show reads due to fetches of non-branch instructions