Computer architecture: Tomasulo algorithm has a disadvantage: Only one result can compute per clock per common data bus $($CDB$).$ Consider the hardware configuration and latencies specified below, with the given code sequence, does Tomasulo algorithm stall due to CDB contention? If your answer is yes, please indicate where this occurs in the sequence; if you do not think there is a stall, please explain why.

Assume the following:

$-$ Functional units are not pipelined.

$-$ There is no forwarding between functional units; results are communicated by the CDB$.$

$-$ The execution stage $($EX$)$ does both the effective address calculation and the memory access for loads and stores. Thus, the pipeline is IF$/$ID$/$IS$/$EX$/$WB$.$

$-$ Loads require one clock cycle.

$-$ The issue $($IS$)$ and write$-$back $($WB$)$ result stages each require one clock cycle.

$-$ There are five load buffer slots and five store buffer slots.

$-$ Assume that the Branch on Not Equal to Zero $($BNEZ$)$ instruction requires one clock cycle.

Instruction Sequence:

$11$: ADD.D F$2,$F$4,$F$6$

$12$: ADD R$1,$R$1,$R$2$

$13$: ADD R$1,$R$1,$R$2$

$14$: ADD R$1,$R$1,$R$2$

$15$: ADD R$1,$R$1,$R$2$

$16$: ADD R$1,$R$1,$R$2$

$17$: ADD R$1,$R$1,$R$2$

$18$: ADD R$1,$R$1,$R$2$

That is all the question