Computer organization.

Given the typical MIPS architecture figure, perform a new instruction (store-increment index register). Add any necessary control signal or hardware for those two operation. Show details.

Instruction 125-0l shift Jump address [31-0] left 2 28 26 0 PC +4 [31-28] Add ALU Add result 4 0 Shift left 2 RegDst Jum Branch MemRead MemtoReg Instruction [31-26] Control ALUO MemWrite ALUSrc RegWrite Instruction [25-21Read register 1 Read Instruction [20-16 Read data 1 Read InstructionInstruction [15-111regiter data 2 data Registers PCRead address oregister 2 MWrite Zero ALU ALU result Instruction (31-0] Read Address data memory Ul Write Write Data data memory Instruction [15-0] 16 Sign- 32 ALU control extend Instruction [5-0] Instruction 125-0l shift Jump address [31-0] left 2 28 26 0 PC +4 [31-28] Add ALU Add result 4 0 Shift left 2 RegDst Jum Branch MemRead MemtoReg Instruction [31-26] Control ALUO MemWrite ALUSrc RegWrite Instruction [25-21Read register 1 Read Instruction [20-16 Read data 1 Read InstructionInstruction [15-111regiter data 2 data Registers PCRead address oregister 2 MWrite Zero ALU ALU result Instruction (31-0] Read Address data memory Ul Write Write Data data memory Instruction [15-0] 16 Sign- 32 ALU control extend Instruction [5-0]