Exercise 4. [20 Marks] Consider a 32-bit computer with a simplified memory hierarchy. This hierarchy contains a single cache and an unbounded backing memory. The cache is direct-mapped with 8 sets and a capacity of 128 bytes. Consider also the following sequence of memory word addresses. 5, 7, 9, 36, 13, 12, 24, 38, 17, 18, 6, 20, 40, 60, 10, 4 (a) Determine, in binary notation, the set index and block offset for each address in the above sequence. Include the byte offset as part of the block offset. Assume the cache is initially empty. During the sequence of address accesses above, determine if each reference results in a cache hit or a cache miss. If the reference results in a cache miss, determine which type of cache miss occurs: cold, conflict, or capacity. You may complete the below table in order to answer this question. Index Block Offset Hit or Miss Type of Miss Address 5 7 9 36 13 12 24 38 17 18 6 20 40 60 10 4 (b) Create a table which resembles this cache's configuration. Fill that table such that it corresponds to the cache's contents after all addresses in the above sequence have been referenced. (See 3350-L4-CacheExample.pdf")