Consider a 32-bit microprocessor that has an on-chip, 32-KByte direct mapping cache. Assume that the cache has a cache line size of eight 32-bit words.

a. What is the bit structure of the cache scheme? (NOTE: requesting the number of bits used for each field in the scheme)

b. What is the number of blocks mapped into the same line?

c. Determine the lines that the following addresses are mapped into: ABCDE8FA, CBC178F8, and ABCDE8CD.

d. Proposed three addresses that will produce thrashing effect.

e. Draw a block diagram of the HW implementation this mechanism using digital logic (gates, comparators and multiplexers) of the cache memory showing the organization and how the different fields are used to determine the cache hit/miss.