Consider a 5 staged pipelined MIPS processor where its operation is divided into 5 stages. Each stage is timed as shown below. What is the clock period of this processor Execution Time Stage: Fetch Decode Execute Memory WriteBack 341 ns Time: 137 ns 166 ns 274ns 92 ns a. 341.00 ns b. None of the options c. 202.00 ns d. 1010.00 ns e. 92.00 ns