Consider a byte addressing architecture with $64-$bit memory addresses. $4\mathrm{.}1(5$ points$)$ Which bits of the address would be used in the tag, index and offset in a direct$-$mapped cache with $5121-$word blocks? $4\mathrm{.}2(5$ points$)$ Which bits of the address would be used in the tag, index and offset in a direct$-$mapped cache with $648-$word blocks? $4\mathrm{.}3(5$ points$)$ What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases? $4\mathrm{.}4(5$ points$)$ Which bits of the address would be used in the tag, index and offset in a two$-$way set associative cache with $1-$word blocks and a total capacity of $512$ words.