Consider a CPU$-$Memory system having L$1$ cache, L$2$ cache and main memory. Suppose that in $1000$ memory references there are $40$ misses in the first$-$level cache and $20$ mi the miss penalty from $L2$ cache to Memory is $100$ clock cycles, the hit time of $L2$ cache is $10$ clock cycles, the Hit time of $L1$ cache is $1$ clock cycle. What is average memory ac Ignore the impact of writes or any other sources of latencies.

$5$ cycles

$2\mathrm{.}4$ cycles

$3\mathrm{.}4$ cycles

$2\mathrm{.}5$ cycles