Question: Consider a direct - mapped cache design with a 6 4 - bit address. The following bits of the address are used to access the

Consider a direct-mapped cache design with a 64-bit address. The following bits of the address are used to access the cache.
Tag Index Offset
63-1312-54-0
a. What is the cache block size?
b. How many blocks does the cache have?
c. What is the ratio between the total bits required for such a cache implementation over the data storage bits

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