Question: Consider a memory hierachy with two cache levels L1 and L2, L1 with a miss rate of 9% and L2 with a miss rate of

Consider a memory hierachy with two cache levels L1 and L2, L1 with a miss rate of 9% and L2 with a miss rate of 4% and an access time of 8 clock cycles. The main memory has an access time of 40 clock cycles. Assume that 29% of the instructions are loads and stores. The execution CPI is 1.0.
Compute the value for the CPI taking into account the memory stall cycles

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