Consider a memory system with a level $1$ cache of $32KB$ and DRAM of $512MB$ with

the processor operating at $1GHz.$ The latency to $L1$ cache is one cycle and the latency to

DRAM is $100$ cycles. In each memory cycle, the processor fetches four words $($cache line

size is four words$).$ What is the peak achievable performance of a dot product of two

vectors? Note: Where necessary, assume an optimal cache placement policy.

$/*$ dot product loop $*/$

for $+=a[i]$