Consider a MIPS 5-stage pipeline with the execution stage consisting of 1-lnteger, 1-FP multiply, 1-FP adder and 1-FP divide shown below. Integer operations takes 1 clock cycle, FP/integer multiply takes 7 clock cycles, FP adder takes 4 clock cycles and FP divide takes 2-5 clock cycles. FP load is similar to an integer load operation EX (integer) EX FP/intege Multiply) IF ID MEMWB EX (FP Adder EX FP/Intege Divider) FO, 0 (R2) F4, 0 (R2) FO, FO, F4 F2, FO, F2 R2 , R2, #8 R3, R3, #8 R5, R4, R2 R5, Loop Loop: L.D L.D MULT. D ADD.D ADDI ADDI SUB BNZ Assume that the initial value of R4 is R2+792 Consider a MIPS 5-stage pipeline with the execution stage consisting of 1-lnteger, 1-FP multiply, 1-FP adder and 1-FP divide shown below. Integer operations takes 1 clock cycle, FP/integer multiply takes 7 clock cycles, FP adder takes 4 clock cycles and FP divide takes 2-5 clock cycles. FP load is similar to an integer load operation EX (integer) EX FP/intege Multiply) IF ID MEMWB EX (FP Adder EX FP/Intege Divider) FO, 0 (R2) F4, 0 (R2) FO, FO, F4 F2, FO, F2 R2 , R2, #8 R3, R3, #8 R5, R4, R2 R5, Loop Loop: L.D L.D MULT. D ADD.D ADDI ADDI SUB BNZ Assume that the initial value of R4 is R2+792