consider a no$-$pipeline processor that takes $5$ns to execute an instruction. It the takes $0\mathrm{.}2$ns to latch its result onto latches. Using a pipeline processor with five equal sequential stages, we implement the same instruction. Note that the non$-$pipeline processor will latch the result at the end of the instruction execution while the pipeline processor will latch the results of each stage during instruction execution. Assuming that there are no stalls$/$hazards in the pipeline, answer the following questions. i$.$ what is the clock cycle time and clock speed rate for the non$-$pipeline processor? ii$.$ What is the clock cycle time and clock speed rate for the pipeline processor? iii. what are the instructions per cycle for the non$-$pipeline processor? iv$.$ what is the latency of each instruction for the non$-$pipeline and pipeline processor? v$.$ what is the speedup from pipelining?