Consider a non$-$pipelined processor with a clock rate of $xGHz$ and average cycles per instruction of $Z.$

The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline

delay, the clock speed is reduced to $YGHz.$

$x=2\mathrm{.}5$

$Y=2$

$Z=5$

Assume there are no stalls in the pipeline. The speed up in throughput $($Instruction per sec$)$ achieved after pipelining

the processor is$.$

Note: Answer to two decimal place. Example $(3\mathrm{.}755$ make it $3\mathrm{.}75)$