Part 01

Draw It Out

Task: What will the results be after a set of instructions has been executed?

Assignment: What will be stored in the registers, the IP, and the IR after the following five instructions have been processed, starting with the instruction at the address 1000?

RAM address Instruction 1000 Load a 7 into register 2 1001 Load a 5 into register 4 1002 Load a 12 into register 3 1003 Add register 3 to register 2, Putting results in register 1 1004 Subtract register 4 from register 1, Putting results in register 5

Question 2. A four stage pipeline has the stage delays as 150, 120, 160 and 140 ns respectively. Registers are used between the stages and have a delay of 5 ns each. Assuming constant clocking rate, the total time taken to process 1000 data items on the pipeline will be:

Question 3. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of 4. The same processor is upgraded to a pipelined processor with five stages but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume there are no stalls in the pipeline. The speed up achieved in this pipelined processor is: