Consider a pipelined machine operating at $200$ Mhz$,$ with the following program execution characteristics.

Tabellenspalten von links nach rechts und von oben nach unten:

Instruction class, CPI, Frequency, R$-$Type $+$ Immediate, $3,55\%,$ lw$,4,25\%,$ sw$,5,10\%,$ beq, $2,7\%,$ j$,3,3\%$

The designers decided to add a new addressing mode wherein registers can be automatically incremented by $4.$ Therefore a sequence such as code block $1$ below can be replaced by the instruction shown in code block $2.$ We have $10\%$ of the sw instructions affected in this manner. Assuming that the cycle time does not change and the new instruction also takes $5$ cycles, what is the speedup produced by the use of this new addressing mode?

sw Sto, $0($St$1)$

addi $t$1,$ St$1,4$

code block $1$

becomes

sw Sto, $($Stl$)+$

code block $2$