Question: Consider a pipelined processor with a 5 - stage pipeline that is perfectly balanced. For simplicity, assume that all instructions take 5 cycles. The dynamic

Consider a pipelined processor with a 5-stage pipeline that is perfectly
balanced. For simplicity, assume that all instructions take 5 cycles. The dynamic instruction count by
type, as a percentage of the total, is as follows:
-10% stores -25% loads -15% branches -50% ALU
(a) What is the ideal speedup due to pipelining for this processor compared with unpipelined single-cycle
processor?

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