Consider a processor with a 4-way set-associative cache with one -word cache blocks and a total cache size of 16 words. The cache uses a least recently used (LRU) replacement policy and is initially empty. The following sequence of decimal word address references is seen by the cache:2, 86, 53, 61, 29, 37, 28, 2, 45, 20, 6, 22, 14, 6, 53, 29, 78, 4, 22, 70, 61, 54, 78, 45, 2, 61, 37, 45, 6, 29, 28. Identify whether each address reference is a hit or a miss show the final cache contents