Consider a word address sequence: 0, 8, 0, 6, 8, 7, 4 for a 4-block cache designed in 3 different ways, viz., Direct mapped, 2-way set-associative, and 4-way set associative. Considering 1-word/block cache design and LRU replacement strategy, enter relevant values in the boxes below. Use binary values, except for the data part in cache (for the data part, use Mem[0] to denote memory content of address 0). Ignore the word/byte offsets, and the valid bit when calculating the number of bits in the Tag field. Helpful Note: With associativity, the number of bits in the tag field generally increases irrespective of whether those extra bits are required or not.

4-way Word address Hit/ Miss Cache content after access Tag Data Tag Data Tag Data Tag Data 0 8 0 6 8 7 4